| 82C201 |
System Control Chip |
Clock generator, Bus Controller, DCL, Wait state logic, BAL, DRAM refresh,
Coprocessor interface, NMI logic |
| 82C202 |
Address decoder |
ROM/RAM decoder, Parity logic, I/O ports decoder |
| 82C203 |
Bus drivers/buffers |
High address bus buffers, Control bus buffers, Port-B system control port,
Port-C system status port |
| 82C204 |
Memory address buffers |
Address bus buffers, RAM address multiplexers, Refresh counter |
| 82C205 |
Data bus buffers |
Data buffers, Parity generator, Parity checker |
| 82C206 |
Integrated peripheral controller |
Two DMA controllers, Two interrupt controllers, Timers, Calendar chip, DMA
page register, configuration register |
| 82C211 |
CPU/Bus controller |
Clock generation, optional AT bus clock, CPU interface, bus control,
wait states |
| 82C212 |
Page interleave and EMS memory controller |
Page mode access with 2-way/4-way interleave, 8 MB max, LIM-EMS 4, Shadow
RAM, HMA remapping |
| 82C215 |
data/Address buffers |
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